1. Field of the Invention
The present invention relates to an electrically programmable non-volatile semiconductor storage device.
2. Description of the Related Art
Recently, an essential need exists for relatively small, heterogeneous-type non-volatile semiconductor storage devices in a semiconductor integrated circuit that may be consolidated on the same chip and that may continually retain the already-described information when the power turned off. Moreover, such demands have increased for redundancy application in mass storage memory such as DRAM or SRAM, for storage application for a code including an encryption key, for management application in manufacturing history, and so on.
Conventionally, a laser fuse has been used as a storage element for a non-volatile semiconductor storage device for these applications (see, for example, Japanese Patent Laid-Open No. (HEI) 9-36234 and 2001-168196). However, when a laser fuse is used, a problem arises that would increase cost for writing because a specially designed fuse blow device and the associated blow process are required accordingly. In addition, since the minimum dimension of a laser fuse is determined by the wavelength of the laser beam in use, it does not keep in step with refinement of other semiconductor devices, causing a problem that the percentage of area occupied by a laser fuse could gradually increase. Further, since a laser is used to perform write operation, a laser fuse needs to be exposed when writing. As a result, if data needs to be written after packaging, such a laser fuse may not be available. Therefore, recent years have raised hopes in electrically writable non-volatile elements.
As an example of such electrically writable non-volatile semiconductor storage elements, an anti-fuse element with a MOS structure is known in the art (see, for example, Japanese Patent Laid-Open No. 2001-168196 and 2003-115537). In a data write operation onto the element, data is written by applying a high-voltage to both ends of the element to break down an insulating film. On the other hand, in data read operation, such a low voltage is first applied to both ends of the anti-fuse element that would not break down the insulating film. Then, detection is made to determine whether the insulating film is broken down according to the amount of current, large or small, that flows into the anti-fuse, thereby reading one-bit information. As can be seen from the above, the anti-fuse element is one of the most promising non-volatile storage elements for future use, since it has such a simple data read/write operation that requires only voltage application to the both ends of the element.
The anti-fuse element provides a feature that no special manufacturing process is involved. This feature provides the benefits of reduced manufacturing cost. In addition, the anti-fuse element has the advantages of no performance degradation in other semiconductor devices that are consolidated on the same chip, including high-speed transistors for configuring logic gates and refined memory elements such as DRAM or SRAM.
However, as developments in semiconductor storage devices being directed to further refinement, some problems have recently been observed in utilizing these anti-fuse elements with MOS structures. There have been developed further refined semiconductor devices as well as thinner gate insulation films for providing further integrated and lower power-consumption semiconductor integrated circuits. Generally, a leakage current that flows into an insulation film exponentially increases as the device becomes thinner. Since the anti-fuse elements uses a state before breaking down the gate insulation film as a state of retaining 0 data, a problem arises that could lead to degradation of 0-data retaining characteristics as the leakage current increases in a corresponding gate insulation film.
It should be noted here that the amount of leakage current in the gate insulation film mentioned above is so small that poses no problem in normal usage such as for use in logic gates. Therefore, it is assumed that there will continue to be thinner gate insulation films and so will the leakage current increase accordingly. It is conceivable that a specialized process is applied in manufacturing insulation films of the anti-fuse element for mitigating the associated degradation of 0-data retaining characteristics in the anti-fuse elements. However, this could result in increased manufacturing cost and not applicable with the intended usage of anti-fuse elements. That is, the degradation of 0-data retaining characteristics associated with the thinner gate insulation films must be accepted in the anti-fuse elements.
Effective means for accepting such degradation of 0-data retaining characteristics associated with the thinner gate insulation films include detecting storage cells with poor 0-data retaining characteristics and replacing those with redundant cells. Thus, there is a need for a 0-margin test that detects such a storage cell with poor 0-data retaining characteristics. As described above, since the degradation of 0-data retaining characteristics results from the leakage current in the gate insulation films, it is assumed that the current value is to be significantly small. Therefore, the 0-margin test requires highly sensitive current detection capabilities to detect minute currents. Further, as the leakage current in the gate insulation film is sensitive to, e.g., variations in the film thickness of each gate oxide film, it is greatly affected by external factors. Accordingly, a wide range of current detection capabilities is required for the 0-margin test. That is, it is an important issue to enable current thresholds of the 0-margin test to be set in a “broad and highly accurate” fashion during 0-margin test operation.
For example, if an average of the leakage current in the gate insulation film of the anti-fuse element is as small as less than 1 nA, then, depending on individual differences, such an anti-fuse element with more than 50 nA appears at about several ppm. Under these circumstances, it is desirable that a current threshold to be used in a storage cell with poor 0-data retaining characteristics, i.e., the one used in 0-margin test, is set to not less than 50 nA. If the fraction defective is on the order of several ppm, then such defects may be repaired by a relatively small redundant circuit. Further, the leakage current in the gate insulation film of the anti-fuse element is so sensitive to variations in the film thickness of each gate oxide film that it could increase by a factor of 5 when the corresponding thinned gate is processed to be about only 10% thinner. In this case, the current threshold used in 0-margin test may be set to greater than 50 nA to suppress the rise in fraction defective. Conversely, if the thinned gate is processed to be about 10% thinner, the current threshold used in 0-margin test may be set to less than 50 nA, which may, as described below, enable the margin for 1-data retaining characteristics to be set larger.
Meanwhile, the upper limit of the current threshold used in 0-margin test is restricted by the characteristics of read current in anti-fuse elements that retain 1 data, as will be discussed further below.
The read current of anti-fuse elements in which the gate insulation film was broken down, i.e., the read current of those retaining 1 data, is expected to be on the order of 100 μA. However, since there would actually be large individual differences, those anti-fuse elements may often appear with respective read currents less than 10 μA.
Under these circumstances, in order to ensure the read current of anti-fuse elements that retain 1 data, such a verify-rewrite technique is proposed that detects anti-fuse elements with insufficient read currents by comparing with a current threshold of a predefined 1-margin test, e.g., 10 μA, and executes additional program (see, for example, Japanese Patent Laid-Open No. 2005-302091). With this technique, the amount of read current for anti-fuse elements that retain 1 data may be set, e.g., to not less than 10 μA. However, the effects of this technique are also limited. If the current threshold of 1-margin test is set to more than the capability of itself, those storage cells may appear with respective read currents not exceeding the current threshold of 1-margin test no matter how many times rewrite operations are performed. The appearance of such storage cells is taken as a write operation failure, which could lead to a reliability problem.
In addition, it must be taken into account in setting current thresholds in normal read operation that the read current in those storage cells retaining 1 data have variations in its characteristics due to voltage dependency, environmental temperature dependency, time degradation, or the like. Therefore, as described above, if the current threshold of 1-margin test is set to on the order of 10 μA, then the upper limit of the current threshold for normal read operation is on the order of 1 μA.
The current threshold of 1-margin test and the current threshold for normal read operation are such setting parameters that should be determined by the characteristics of read current for Corresponding anti-fuse elements after programming. It is not so important to ensure accuracy in the current thresholds of 1-margin test and normal read operation, but rather, it is necessary to keep a constant ratio between these two current thresholds. It is also necessary to implement no complicated timing control in using non-volatile semiconductor storage devices. Therefore, it is desirable that the current thresholds of the current threshold of 1-margin test and normal read operation are set by circuit constants of the circuits that configure a corresponding non-volatile semiconductor storage device.
On the other hand, the current threshold used in 0-margin test may be set in a very wide range from the bottom of a distribution of leakage currents in the gate insulation film of the anti-fuse element, e.g., 50 nA, to the current threshold in normal read operation, e.g., less than 1 μA. Moreover, the leakage current in the gate insulation film of the anti-fuse element is greatly affected by the thickness of each gate insulation film. Further, the acceptable ratio of defect differs greatly depending on the usage of non-volatile semiconductor storage devices and its associated storage capacity, as well as means and magnitude of redundant circuits for use in repair of defective devices. To accommodate these circumstances, setting means is required that enables current thresholds for 0-margin test to be set in a highly flexible manner.
In order to set the current thresholds used in 0-margin test, it is also necessary to obtain distribution data for leakage currents in the gate insulation film of the anti-fuse element. Indeed, a significant amount of accurately measured data may be obtained from measurement of leakage current of anti-fuse elements implemented on a non-volatile semiconductor storage device. Although the 0-margin test features are efficient to achieve such measurements, it is necessary to provide a much wider range of current thresholds for 0-margin test and highly-sensitive current detection capabilities, e.g., up to 10 pA. Further, there is a need for means for setting current thresholds for 0-margin test at a narrow interval.